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Eduardo Boemo Scalvinoni Universidad Autónoma de Madrid Profesor Titular de
Arquitectura y Tecnología de Computadores |
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Teaching: Year 1 Telecom Degree Coordination Past teaching: AE Research Seminars Publications: R&D / Industry: Digital System Lab Technical Conferences: Editorial Boards: Sabbatical year, Master or PhD Degree at the
UAM? |
Short Bio: Titular Professor on Logic Design and ASIC Design at
the School of Engineering (EPS), Universidad Autónoma
de Madrid, Spain (UAM).
Honorary professor at CAECE University, Argentine. Ph.D. in Telecom
Engineering from the Universidad Politécnica de Madrid, Spain, and
Electrical Engineer degree from the Universidad
Nacional de Mar del Plata, Argentine.
Associated Professor at the ETSI Telecomunicación (UPM) from 1989 to 1996. General Chairman of FPL 2006, SPL (2008, 2007,
and 2006 editions), JCRA (2007 and
2003 editions). Director of the EUROFORM Spanish Pole, an organization to provide professional training
on FPGAs. Member of Technical Committees of FPGA conferences. Associate Editor of
the ACM Transactions on Reconfigurable Systems. Member of the Editorial Board of the Journal of Low-Power Electronics. Co-editor of the Special Issue on FPGAs of the IET Computer & Digital Techniques Journal
(July, 2007). Research lines, papers, Ph.D.Thesis, seminars and courses are focused on
FPGA Design Methodologies and Application. In particular:
Area–Time-Power-Thermal Optimization, Self-Timed Synchronization, and E.E. Education. Address: School of Engineering Office C225 - Lab C115 Universidad Autónoma de Madrid Ctra. de Colmenar Km. 15 28049 Madrid - Spain Phone: +34 91 497 6213 Fax: +34 91 497 4574 e-mail: eduardo.boemo at uam.es
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