Titular Professor on
Logic Design and
ASIC
Design at the School of Engineering (EPS), Universidad Autónoma de
Madrid, Spain (UAM). Invitated professor
in several
seminars and courses at
universities and research centers. Honorary professor at
CAECE
University, Argentine. Ph.D. in Telecom. Engineering
from the Universidad Politécnica
de Madrid, Spain, and Electrical Engineer degree from the
Universidad Nacional de Mar del Plata, Argentine.
General Chairman of
six conferences on FPGAs:
FPL 2006,
SPL (2008,
2007,
and 2006
editions),
JCRA (2007 and
2003 editions). Director of
the EUROFORM Spanish Pole,
an organization to provide professional training on FPGAs. Member of
some Technical Committees
of FPGA conferences.
Associate Editor of the
ACM Transactions on Reconfigurable
Systems. Member of the Editorial Board of the
Journal of Low-Power
Electronics. Co-editor of the
Special Issue on FPGAs of the IET Computer & Digital Techniques
Journal (July, 2007).
Current research areas are focused on FPGA-based systems; in
particular: Area-Time-Power Optimization, Thermal Testing,
Self-Timed Synchronization,
E.E. Education, Custom DSPs, and Robotics, where several papers
and Ph.D. Thesis have been published.