Eduardo Boemo

1. S. Lopez-Buedo, J. Garrido, and E. Boemo, "Dynamically Inserting, Operating, and Eliminating Thermal Sensors of FPGA-based Systems", IEEE Transactions on Components and Packaging Technologies (CPM), Vol.25, Nº4, pp.561-566, December 2002. [PDF]

2. S. Lopez-Buedo, J. Garrido and E. Boemo, "Thermal Testing on Reconfigurable Computers", IEEE Design & Test of Computers, pp.84-90, January-March 2000. [PDF]

3. Sergio Lopez-Buedo and Eduardo Boemo, "Making Visible the Thermal Behaviour of Embedded
Microprocessors on FPGAs. A Progress Report", Proc. ACM FPGA 2004, Feb 22-24, Monterrey, USA. ACM Press:2004. [PDF]

4. E. Boemo and S. Lopez-Buedo, "Themal Monitoring on FPGAs using Ring-Oscillators", Lecture Notes in Computer Science, No.1304, pp.69-78, Berlin: Springer-Verlag, 1997. [PDF]

5. S. Lopez-Buedo, P. Pernas and E. Boemo, "Run-time Reconfiguration to Check Temperature in Custom Computers: An Application of JBIT Technology", Lecture Notes in Computer Science, Vol.2438, pp.162-170, Berlin: Springer-Verlag, 2002. [PDF]

6. E. Boemo and S. Lopez-Buedo, "Thermal Verification on FPGAs", Invitated Talk, Proc. 23rd Norchip Conference, pp. 48-53, Oulu Finland, November 2005, IEEE Press, 2005. [PDF]

7. S. Lopez-Buedo, J. Garrido and E. Boemo, "Thermal Testing on Programmable Logic Devices", Proc. 1998 IEEE ISCAS (Int. Symp. on Circuits and Systems), Vol.II, pp.240-243, Monterey, June 1998. [PDF]

8. Sergio Lopez-Buedo, Javier Garrido, and Eduardo Boemo, "Measurement of FPGA Die Temperature Using Run-time Reconfiguration", Proc. Therminic 2001 (Int. Workshop on Thermal Investigations of ICs and Systems), pp.168-173. Paris, September 24-26. TIMA-CMP 2001. ISBN: 2-913329-72-1. [PDF]

9. S. Lopez-Buedo and E. Boemo, "A Method for Temperature Measurement on Reconfigurable Systems", Proc. XII DCIS Conference (Design of Circuit and Integrated Systems), pp.727-730, Universidad de Sevilla: November 1997. [PDF]

Custom DSPs and Computer Arithmetics:

1. M. Martinez-Peiro, E. Boemo, and L. Wanhammar, "Design of High Speed Multiplierless Filters using a Nonrecursive Signed Common Sub-expression Algorithm", IEEE Trans. on Circuits and Systems Part II: Analog and Digital Signal Processing, Vol.49, No.3, pp.196-203, March 2002. [PDF]

2. J, Valls and E. Boemo, "Efficient fpga-implementation of two's complement digit-serial/parallel multipliers", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume: 50 Issue: 6 , Page(s): 317 -322, June 2003. [PDF]

3. J. Valls, M. Martinez-Peiro, T. Sansaloni, and E. Boemo, "A Study about FPGA-based Digital Filters", Proc. 1998 IEEE SIPS (IEEE Workshop on VLSI Signal Processing: Design and Implementation), pp.191-201, Boston, Oct.1998. [PDF]

4. E. Boemo, F. Barbero, J. Faura, J. Jauregui and J. Meneses, "Programmable Real-Time FIR-filter Integrated Circuit", in Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, J. Schewel (C.E.), Philadelphia. Proc. SPIE 2607, pp.22-29, October 1995. [PDF]

5. J. Valls, M. Martinez-Peiro, T. Sansaloni, and E. Boemo, "Fast FPGA-Based Pipelined Digit-Serial/Parallel Multipliers", Proc. 1999 IEEE ISCAS (Int. Symp. on Circuits and Systems), Volumen I, pp.482-485, Orlando, Florida, May 1999. [PDF]

6. J. Valls, M. Martinez-Peiro, T. Sansaloni, and E. Boemo, "Design and FPGA Implementation of Digit-Serial FIR Filters", Proc. 1998 IEEE ICECS'98 (5th IEEE International Conference on Electronics, Circuits and Systems), Vol.2, pp.191-194, Lisboa, 7-10 Sept. 1998. [PDF]

7. M. Martinez-Peiro, J. Valls, T. Sansaloni, A. Pascual and E. Boemo, "A Comparison between Lattice, Cascade and Direct-form FIR Filter Structures by using a FPGA Bit-serial Distributed Arithmetic Implementation", Proc. 1999 IEEE ICECS (6th International Conference on Electronics, Circuits and Systems), Vol.1, pp.241-244, Paphos, Cyprus, September 5-8, 1999. [PDF]

8. J. Valls, M. Martinez-Peiro, T. Sansaloni y E. Boemo, "Custom Digit-Serial DSP on Altera FPGAs", Proc. XIII DCIS Conference (Design of Circuit and Integrated Systems), Madrid, Universidad Carlos III: November 1998.

9. M. Martinez-Peiro, J. Valls, T. Sansaloni y E. Boemo, "High-Level Synthesis of Custom DSP Blocks using Distributed Arithmetic", Proc. XIII DCIS Conference (Design of Circuit and Integrated Systems), Madrid, Universidad Carlos III: November 1998.

10. G. Sutter, J. Deschamps, and E. Boemo, "Area-Time-Power of Modular Multipliers implemented in FPGA", Jornadas de Computación Reconfigurable y Aplicaciones, JCRA 2004, Barcelona, España, 13-15 de Septiembre de 2004. [PDF].

11. C. Sanz, E. Boemo, J. Moran, S. Alexandres and J. Meneses. "Transformation of Digital Video Television to CCITT H.261 Format for Video Conference Coding", Proc. VIII DCIS Conference (Design of Circuit and Integrated Systems), Universidad de Malaga: November 1993. (in spanish).

1. C. Sanz, J. Moran, E. Boemo, S. Alexandres and J. Meneses. "Development of a Video Telephony Circuit for Chrominance Component Compression", Proc.VIII DCIS Conference (Design of Circuit and Integrated Systems), pp.369-375, Universidad de Malaga, November 1993. (in spanish).

2. I. González, F. Gomez, S. Lopez-Buedo, J. I. Martinez, J. Deschamps, E. Boemo, and J. Martinez, "Implementación del Algoritmo Criptográfico IDEA en Virtex usando JBits", Proc. JCRA 2002 (II Jornadas de Computación Reconfigurable y Aplicaciones), pp.155-160, Universidad de Granada: Septiembre 2002.

3. M. Martínez-Peiro, J. Valls, T. Sansaloni, and E. Boemo, "FPGA-based Methodology to design digital FIR Filters using Distributed Arithmetic", Proc. XIII DCIS Conference (Design of Circuit and Integrated Systems), Madrid, Universidad Carlos III: November 1998. [PDF]

4. M. Martinez-Peiro, J.Valls and E. Boemo, "On the Design of FPGA-based Multioperand Pipeline Adders", Proc.XII DCIS Conference (Design of Circuit and Integrated Systems) pp.701 - 706, Universidad de Sevilla: November 1997.

5. E. Boemo, E. Juarez and J. Meneses. "Taxonomy of Multipliers", Proc.VIII DCIS Conference (Design of Circuit and Integrated Systems), pp.185-190, Universidad de Malaga, November 1993. (in spanish). [PDF]

6. C. Gayoso, A. Garcia, C. Gonzalez, L. Arnone, J. Garcia, and E. Boemo, "Estudio sobre el diseño de sumadores en aritmética de residuos en lógica programable", Proc. JCRA 2002 (II Jornadas de Computación Reconfigurable y Aplicaciones), pp.203-207, Universidad de Granada: Septiembre 2002.

High-Speed Digital Design:

1. E. Boemo, S. Lopez-Buedo, and J. Meneses, "Some Experiments about Wave Pipelining on FPGAs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.6, No.2, June 1998. [PDF]

2. E. Boemo, S. Lopez-Buedo, and J. Meneses, "The Wave Pipeline Effect on LUT-based FPGA Architectures", Proc 1996 ACM Int. Symposium on FPGAs, Monterey, pp.45-50. New York: ACM, February 1996. [PDF]

3. J. Arechabala, E. Boemo, F. Moreno, J. Meneses and C. Lopez-Barrio, "Full Systolic Binary Multiplier". IEE Proceeding. Part G. Vol.139, No.2, pp.188-190. April 1992. [PDF]

4. E. Boemo, S. Lopez-Buedo, and J. Meneses, "Wave Pipelines via Look-Up Tables", Proc. 1996 IEEE ISCAS (Int. Symp. on Circuits and Systems), Atlanta, Vol.IV, pp.185-188. Piscataway, NJ: IEEE Press, 1996 [PDF]

5. E. Boemo, S. Lopez-Buedo, N. Acosta, and E. Todorovich, "Local versus Global Interconnections in Pipelined Arrays: An Example of the Interaction between Architecture and Technology", Proc. XIV DCIS Conference (Design of Circuit and Integrated Systems), pp.181-186, Palma de Mallorca, Spain, November 1999. [PDF]

6. E. Boemo, S. Lopez-Buedo, E. Todorovich, and N. Acosta, "Logic Depth and the Determinism of Place-Route Tools. Some Experiments on FPGAs", Proc. VI Iberchip Workshop, pp.280-285, Sao Paulo, Brazil, 16-18 March, 2000 (in spanish). [PDF]

7. E. Boemo, J. Jauregui, C. Santos, F. Moreno and J. Meneses, "Learning Pipelined Arrays Trade-offs using Standard Cells", Proc. Fifth Eurochip Workshop on VLSI Design Training, pp.353-358. Dresden, October 1994.

8. E. Boemo, S. Lopez-Buedo, and J. Meneses, "Fast Prototyping of Maximum-Speed, Minimum-Latency Binary Multipliers", Proc. XI DCIS Conference (Design of Circuit and Integrated Systems), pp.93-98, Universitat Politecnica de Catalunya, Barcelona: November 1996.

9. E. Boemo, G. Gonzalez de Rivera, S. Lopez-Buedo and J. Meneses, "An Study about Pipelining on FPGAs", Proc. IX DCIS Conference (Design of Circuit and Integrated Systems), pp.549-554, Maspalomas, Universidad de Las Palmas de Gran Canarias: November 1994 (in spanish).

10. E. Todorovich, N. Acosta and E. Boemo, "A Tool for the Analysis of Interconnection Delays on FPGAs", Proc. V Workshop IBERCHIP, Lima, Peru, March 1-3, 1999. (In spanish). [PDF]

11. J. Arechabala, E. Boemo and J. Meneses, "Multiplicador Binario Sistólico", Proc.VI DCIS Conference (Design of Circuit and Integrated Systems), pp. 113-117, Universidad de Cantabria, Santander: November 1991.

12. J. Arechabala, E. Boemo and J. Meneses, "A Systolic Arrays Simulator Framework", Proc. VI DCIS Conference (Design of Circuit and Integrated Systems), pp.303-306, Universidad de Cantabria, Santander: November 1991 (in spanish).

Low-Power Digital Design (see also Thermal Testing on FPGAs):

1. E. Boemo, G. Gonzalez de Rivera, S.Lopez-Buedo and J. Meneses, "Some Notes on Power Management on FPGAs", Lecture Notes in Computer Science, No.975, pp.149-157. Berlin: Springer-Verlag 1995. [PDF]

2. G. Sutter, E. Todorvich, S. Lopez- Buedo, and E. Boemo, "FSM Decomposition for Low Power in FPGA", Lecture Notes in Computer Science, Vol.2438, pp.350-359. Berlin: Springer-Verlag 2002. [PDF]

3. G. Sutter, E. Todorovich, S. Lopez-Buedo, and E. Boemo, "Low-Power FSMs in FPGA: Encoding Alternatives", Lecture Notes in Computer Science, Vol.2451, pp.363-370, Berlin: Springer-Verlag 2002. [PDF]

4. E. Todorovich, M. Gilabert, G. Sutter, S. Lopez-Buedo, and E. Boemo, “ A Tool for Activity Estimation in FPGAs”, Lecture Notes in Computer Science, Vol.2438, pp.340-349. Berlin: Springer-Verlag 2002. [PDF]

5. E. Todorovich and E. Boemo, “A-B Nodes Classification for Power Estimation”, Proc. FPL 2006 (16th International Conference on Field Programmable Logic and Applications), Madrid, Spain, August 28-30, 2006. IEEE Press.

6. E. Todorovich, E. Boemo, F. Angarita, and J. Vails, "Statistical power estimation for FPGAs", FPL 2005 (XV International Conference on Field Programmable Logic and Applications), pp.515 - 518, Tampere, Finland, August 2005. IEEE Press. ISBN: 0-7803-9362-7 [PDF]

7. E. Todorovich, E. Boemo, F. Cardells, J. Valls*, “Power Analysis and Estimation Tool integrated with XPower”, Proc. FPGA 2004 (Twelfth ACM International Symposium on Field-Programmable Gate Arrays), Monterey, California, USA, February 22-24, 2004. ISBN 1-58113-829-6.

8. E. Boemo, S. Lopez-Buedo, G. Gonzalez de Rivera, and J. Meneses, "On the Usefulness of Pipelining and Wave Pipelining as Low-Power Design Technique", Proc. PATMOS Fifth Int. Workshop (Power and Timing Modelling for Performance of Integrated Circuits), pp.252-263. Oldenburg: OFFIS, October 1995.

9. G. Gonzalez de Rivera, J. Garrido, and E. Boemo, "Power Audit of an Space-Certified Microprocessor", Proc PATMOS'99 (International Workshop Power and Timing Modeling, Optimization and Simulation), pp.551-556, October 6-8, Kos Island, Greece. [PDF]

10. G. Sutter, J. Deschamps, G. Bioul, and E. Boemo, "Power Aware Dividers in FPGA", Lecture Notes in Computer Science Nº 3254 (Proc. PATMOS 2004 Conference), Springer-Verlag, Berlin:2004. [PDF]

11. E. Boemo, S. Lopez-Buedo, G. Gonzalez de Rivera, and J. Meneses, "Power Budget on FPGAs", Proc.GI-IGT Anwenderprogrammierbare Schaltungen Workshop, pp.59-65, W. Rosenstiel & A. Ditzinger (eds.), Karlsruhe: Forschungszentrum Informatik, University of Karlsruhe, June 1995.

12. F. Angarita, J. Marin-Roig, E. Todorovich, and E. Boemo, “Relación área-potencia en la implementación con aritmética distribuida de un Filtro FIR en FPGA”, Proc. JCRA 2005, pp. 59-63, ISBN: 84-9732-439-0, Granada, 13-16 Septiembre 2005. [PDF]

13. E. Todorovich, A. Holderbeke, N. Acosta, and E. Boemo, “Estimación de Consumo de Potencia en FPGA a través de un Servicio Web”, Jornadas de Computación Reconfigurable y Aplicaciones, JCRA 2004, Barcelona, España, 13-15 de Septiembre de 2004. [PDF]

14. G. Sutter, E. Todorovich,. and E. Boemo, “Design of Power Aware FPGA-based Systems”, Jornadas de Computación Reconfigurable y Aplicaciones, JCRA 2004, Barcelona, España, 13-15 de Septiembre de 2004. [PDF]

15. Sutter G., E Todorovich E., López-Buedo S., and Boemo E., "Logic Depth, Power, and Pipeline Granularity: Updated Results on XC4K and Virtex FPGAs", in Computación Reconfigurable & FPGAs (Proc. III JCRA Workshop), pp.201-207, Madrid, September 2003.

16. Todorovich E., Sutter G., and and Boemo E., "Estimación de Actividad para FPGA Basada en una Técnica Estadística", in Computación Reconfigurable & FPGAs (Proc. III JCRA Workshop), pp.217-224, Madrid, September 2003.

17. E. Boemo and G. Sutter, "Permutación de los Datos de Entrada como Estrategia de Diseño de Bajo Consumo: Algunos Ejemplos en FPGAs", in Computación Reconfigurable & FPGAs (Proc. III JCRA Workshop), pp.225-232, Madrid, September 2003.

18. J. Rius-Vazquez, E. Boemo, A. Peidro-Palanca, S. Manich-Bou and R. Rodriguez-Montañes, "Measuring Power and Energy of CMOS CIrcuits: A Comparative Analysis", Proceedings DCIS 2003 (XVIII Conference on Design of Circuits and Integrated Systems), pp. 89-94, Ciudad Real, November 2003. ISBN: 84-87087-40-X [PDF]

19. E. Todorovich, G. Sutter, N. Acosta, E. Boemo and S. Lopez-Buedo, "End-user low-power alternatives at topological and physical levels. Some examples on FPGAs", Proc. DCIS'2000 (XV Conference on Design of Circuits and Integrated Systems), pp.640-644, Montpellier, November 21-24, 2000. [PDF]

20. E. Boemo, S. Lopez-Buedo, C. Santos, J. Jauregui and J. Meneses, "Logic Depth and Power Consumption: A Comparative Study Between Standard Cells and FPGAs", Proc. XIII DCIS Conference (Design of Circuit and Integrated Systems), Madrid, Universidad Carlos III: November 1998. [PDF]

21. E. Todorovich, G. Sutter , N. Acosta, E. Boemo y S. Lopez-Buedo, "Relación entre Velocidad y Consumo en FPGAs", Proc. Iberchip 2001 Workshop , Montevideo, Uruguay, 2001. [PDF]

E.E. Education:

1. E. Boemo, J. Meneses, G. Gonzalez. de Rivera and F. Barbero. "Field Programmable Logic in Education. A Case Study", in More FPGAs, W. Moore and W. Luk (eds.), pp.452-457. Abbingdon EE&CS Books: Oxford 1994. [PDF]

2. E. Boemo and J. Meneses. "Learning VLSI using FPGAs", Proc. 23^rd IEEE Frontiers in Education Conference, pp.422-425. Washington, November 6-9, 1993. [PDF]

3. E. Boemo, "A Survey about FPGA Users in Spanish SMEs", Proc 4th European Workshop on Microelectronics Education, Universidad de Vigo, Spain, May 23-24, 2002. In "Microelectronic Education", Editorial Paraninfo, 2002. [PDF]

4. E. Boemo, "Training Requirements in Spanish SMEs in the area of Electronic Design", Proc. TAEE'02 (Five Conf. on Technologies applied to Engineering Education), pp.11-14, Universidad de Las Palmas de Gran Canarias, February 2002. (In Spanish).

5. E. Boemo, J. Meneses, F. Barbero and G. Gonzalez. de Rivera, "Digital Design using LCAs. Results of an Educational Experiment at the School of Telecommunication Engineering - UPM", Proc.VII DCIS Conference (Design of Circuit and Integrated Systems), pp.217-221, Universidad Politécnica de Madrid: November 1992. (in spanish)

6. E. Boemo, "Computer-Based Tools for Electrical Engineering Education: Some Informal Notes", Invitated Paper, Proc. CAEE'99 (5th International Conference on Computer Aided Engineering Education), pp.7-13, Technical University of Sofia, Bulgaria, September 22-24, 1999. [PDF]

7. F. Moreno, E. Boemo, J. Meneses and C. Lopez Barrio, "A Teaching Experience on VLSI at the Technical University of Madrid". Proceeding Third Eurochip Workshop. pp.60-66. Grenoble, September 1992. [PDF]

8. A. Santos, E. Boemo, J. Faura, and J. Meneses, "Microcontrollers in Education", Proc. IEEE 24^th Frontiers on Education Conference, pp.378-383, San Jose (Cal.), 1994. [PDF]

9. E. Boemo, F. Barbero and J. Meneses, "Software Security Strategies for PC-based Educational Laboratories: A Case Study", Proc. 23^rd IEEE Frontiers in Education Conference, pp.815. Washington, November 6-9, 1993. [PDF]

10. E. Boemo, F. Barbero and J. Meneses, "Kipitwel, a Security Program for Educational Laboratories", Proc. CAEE'93 (International Conference on Computer Aided Engineering Education), pp.247-252, Technical University of Bucharest, September 1993.

11. J. Gonzalez, P. Haya, S. Lopez-Buerdo, and E. Boemo, "Tarjeta entrenadora para FPGA, basada en un hardware abierto", Seminario Hispabot 2003, Alcalá de Henares, Mayo 2003.

12. M. Romero, G. Gonzalez de Rivera and E. Boemo, "Computed-Aided Digital Electronic Course", Proc. TAEE'96 (Second Conf. on Technologies applied to Engineering Education), pp.144-148, Universidad de Sevilla: September 1996 (in spanish).

13. I. Pérez, F. Barbero and E. Boemo, "Window-based Courseware Generator", Proc. TAEE'94 Conference (Technologies applied to Engineering Education), pp.313-321. Universidad Politécnica de Madrid: Madrid, July 1994. (in spanish).

14. A. Santos, E. Boemo, J. Faura, and A. Vilallonga, "Microcontrollers: A Distance-Education Laboratoy", Proc.TAEE'94 Conference (Technologies applied to Engineering Education), pp.421-428, Universidad Politecnica de Madrid, July 1994. (in spanish).

Self-Timed Systems:

1. E. Boemo, J. Herrera and J. Meneses, "Logic Depth and Power Consumption in Self-timed Circuits: A Case-study", Proc. 4th ACiD (Asynchronous Circuit Design) Workshop, Grenoble: TIMA Laboratory, Feb.2000. [PDF]

2. Boemo E. and Ortega S., "Sincronización Self-Timed: Protocolos de 2 Fases", in Computación Reconfigurable & FPGAs (Proc. III JCRA Workshop), pp.503-516, Madrid, September 2003. [PDF]

3. S. Ortega-Cisneros, J. Raygoza-Panduro, J. Suardíaz-Muro, and E. Boemo, "Rapid prototyping of a Self-Timed ALU with FPGAs", Proc. ReConFig 2005 (2005 International Conference on Reconfigurable Computing and FPGAs), IEEE Press, ISBN 0-7695-2456-7. [PDF]

4. J. Raygoza-Panduro, S. Ortega-Cisneros, and E. Boemo, "FPGA implementation of a synchronous and self-timed neuroprocessor", Proc. ReConFig 2005 (2005 International Conference on Reconfigurable Computing and FPGAs), IEEE Press, ISBN 0-7695-2456-7. [PDF]

5. Ortega S and Boemo E., "Sincronización Self-Timed: Protocolos de 4 Fases", in Computación Reconfigurable & FPGAs (Proc. III JCRA Workshop), pp.517-528, Madrid, September 2003. [PDF]

6. S. Ortega, J. Raygoza, G. Sutter, S. López-Buedo, and Boemo E. "Implementación de Circuitos Self-Timed de 2 y 4 Fases en FPGAs", in Computación Reconfigurable & FPGAs (Proc. III JCRA Workshop), pp.407-416, Madrid, September 2003.

7. J. Raygoza-Panduro, J. Ortega-Cisneros, and E. Boemo, "FPGA implementation of a synchronous and self-timed neuroprocessor", Proc. ReConFig 2005 (International Conference on Reconfigurable Computing and FPGAs) , 28-30 Sept. 2005, Mexico. [PDF]

8. S. Ortega-Cisneros, J. Raygoza-Panduro, J. Suardiaz Muro, and E. Boemo, "Rapid prototyping of a self-timed ALU with FPGAs", Proc. ReConFig 2005 (International Conference on Reconfigurable Computing and FPGAs) , 28-30 Sept. 2005, Mexico. [PDF]

9. S. Ortega-Cisneros, J. Raygoza-Panduro, and E. Boemo, "Diseño e Implementación en FPGA de un Microprocesador Self-Timed de 16 bits, utilizando el protocolo de 4 fases", Proc. JCRA 2005 (V Jornadas sobre computación reconfigurable y aplicaciones), pp.407-416 Granada, Septiembre 2005. [PDF]

Robotics and Control:

1. J. González-Gomez, H. Zhang, E. Boemo, J. Zhang, "Locomotion Capabilities of a Modular Robot with Eight Pitch-Yaw-Connecting Modules", Proc. CLAWAR 2006 (9th International Conference on Climbing and Walking Robots), Royal Military Academy, Brussels, Belgium, 11-14 September 2006, Lecture Notes in Computer Science, Springer-Verlag 2006. [PDF]

2. J. González-Gómez and E. Boemo,”Motion of Minimal Configurations of a Modular Robot: Sinusoidal, Lateral Rolling and Lateral Shift” , Proc. CLAWAR 2005 (8th International Conference on Climbing and Walking Robots), London, September 2005, Lecture Notes in Computer Science, Springer-Verlag 2005. [PDF]

3. J. González-Gómez, J, E. Aguayo, and E. Boemo, "Locomotion of a Modular Worm-like Robot using a FPGA-based embedded MicroBlaze Soft-processor", Proc Clawar 2004 (7th International Conference on Climbing and Walking Robots), CSIC, Madrid (Spain). September, 2004, Lecture Notes in Computer Science, Springer-Verlag 2004. [PDF]

4. J. González-Gómez, I. González, F. Gómez and E. Boemo, "Evaluation of a Locomotive Algorithm for Worm-like Robot on FPGA-embedded Processors", Proc. ARC 2006, Lecture Notes in Computer Science, Springer-Verlag 2006. [PDF].

5. J. González-Gómez, J, E. Aguayo, and E. Boemo, "Locomoción de un Robot Ápodo Modular con el Procesador MicroBlaze”, Proc. JCRA04 (IV Jornadas sobre Computación Reconfigurable y Aplicaciones), Escuela Técnica Superior de Ingenierías. Universidad Autónoma de Barcelona, Septiembre 2004. [PDF]

6. J. González-Gómez, I. González, and E. Boemo, "Alternativas Hardware para la Locomoción de un Robot Apodo", in Computación Reconfigurable & FPGAs (Proc. III JCRA Workshop), pp.327-334, Madrid, September 2003. [PDF]

7. E. Aguayo, I. González, and E. Boemo, "Tutorial Xilinx MicroBlaze", Proc. JCRA 2004, Universidad Autónoma de Barcelona, Sept. 2004. [PDF]

8. J. Gonzalez-Gómez, P. Haya, S. Lopez-Buerdo, and E. Boemo, "Tarjeta entrenadora para FPGA, basada en un hardware abierto", Seminario Hispabot 2003, Alcalá de Henares, Mayo 2003.

9. G. González de Rivera, S- Lopez-Buedo, I. Gonzalez, C. Venegas, J. Garrido, and E. Boemo, "GP_BOT: A Hardware para la Enseñanza de Robótica en la Titulación de Ingeniería", Proc. TAEE'02 (Five Conf. on Technologies applied to Engineering Education), pp.67-70, Universidad de Las Palmas de Gran Canarias, February 2002. (In Spanish).

10. G. González de Rivera, C. Venegas, I. Gonzalez, S- Lopez-Buedo, J. Garrido, and E. Boemo, "Control of Access using Chips Cards: An Application Via Internet", Proc. TAEE'02 (Five Conf. on Technologies applied to Engineering Education), pp.81-84, Universidad de Las Palmas de Gran Canarias, February 2002. (In Spanish).

Miscellaneous:

1. N. Bonsfills, J.Raygoza, E. Boemo, J. Garrido, A. Núñez, and E. Gómez-Barrena, "Proprioception in the ACL-ruptured knee: The contribution of the medial collateral ligament and patellar ligament. An in vivo experimental study in the cat", The Knee, Elsevier, to be published in 2007.

2. B. Menendez, R. Martin, A. Grajal, P. Banderas, A. Díaz, G. Sutter, and E. Boemo, "A B2B Initiative for SMEs in the Area of Tools, Construction, and Industrial Hardware", Proc. 2002 eBusiness and eWork Conference, pp.1471-1477. IOS Press: Prague, Oct.2002. ISBN 1-58603-284-4. [PDF]

3. J. Raygoza-Panduro, S. Ortega-Cisneros, E. Boemo, E. Gómez- Barrena, A. Nuñez, and N. Bonsfills, "Implementación de un Sistema de Monitoreo de la Deformación Superficial de los Ligamentos en una Articulación", SOMI Congreso XIX de Instrumentación., Vol 1, Aplicaciones a la Bioelectrónica, Universidad Autónoma del Estado de Hidalgo, Pachuca, Mexico., Octubre 2004. [PDF]

4. J. Raygoza, S. Ortega, E. Gómez, N. Bonsfills, A. Núñez, G. González de Rivera Peces, S. López-Buedo, J. Garrido, and E. Boemo, "Reconocimiento de Patrones de Tensión-Deformación de los Ligamentos de una Articulación", in Computación Reconfigurable & FPGAs (Proc. III JCRA Workshop), pp.417-424, Madrid, September 2003.

5. M. Tosini, G. Acosta, and E. Boemo, “A model of Digital NN for Clima Prediction”, Proc. CACIC 2000 (Argentine VI Conference on Computer Science), Usuahia, Argentine, 3-6 October, 2000 . (In spanish). [PDF]

6. M. Tosini, E. Boemo, and G. Acosta, “NNGen, an automatic system to generate digital NN on FPGAs”, IWS’2001 (VII Iberchip Workshop), Montevideo, Uruguay, 2001. (In spanish). [PDF]

Last update: 29/03/2007