Digital System Laboratory School of Engineering – Universidad Autónoma de Madrid Research & Development Projects

Teaching: CEDG (Logic) Lab CEDG DCSE (ASIC) Beca Excelencia AE High-Speed & Low-Power Design Year 1 Telecom Degree Coordination Invitated Seminars Publications: Papers Books Ph.D. Thesis Advising R&D / Industry: Projects Digital System Lab Euroform Technical Conferences: FPL 2006 SPL 2007 SPL 2006 JCRA 2007 JCRA 2003 Editorial Boards: JOLPE ACM TRETS Are you interested in a PhD Degree at the UAM?

Projects at the EPS - UAM (1996-now) Project Title:  "Efficient Protection of IP Blocks” Duties: Project Director Contractor/Sponsors: TEC Program, Ministry of Science, Spain Partners: Universidad de Granada, Spain Period: Sep 2007 – Sep 2010 Technology: Xilinx FPGAs. Project Title: “MicroBlaze-MicroLinux Embedded System for Industrial Tile Printer”. Duties: Project Director Contractor: Kerajet, Spain Technology: Xilinx FPGAs. Project Title:  " Prototype of a Portable Tripanosoma Cruzi (PDP-TC) Detector" Duties: R&D Engineer Contractor/Sponsors: Banco Santander Central Hispano. Period: Jan 2007 - Dec 2007 Project Title:  "Surlabs: Latin American Regional Laboraroties on FPGA Technology" Duties: Project Director Contractor/Sponsors: Banco Santander Central Hispano, Xilinx Inc., Altera Corp., Hewlett-Packard, CAECE University, Agencia Nacional de Promoción Científica y Técnica, Argentina. Period: March 2005 - 2007 Web page of the project: http://www.ii.uam.es/~mcts/SURLABS.htm and http://www.splconf.org/ Project Title: FPL 2006 Conference Duties: General Chairperson Contractor/Sponsors: Xilinx, Celoxica, Altera, Cesnet, Synplicity, Agilent, Mentor Graphics, Alpha Data, Xjtag. Partners: Universidad Autónoma de Madrid, Technical University of Darmstadt, The Chinese University of Hong Kong Period: Jan 2006 – Dec 2006 Web page of the project: http://arantxa.ii.uam.es/~fpl06/ Project Title:  "Campus Europae. Engineering Comitee" Duties: Chairman Engineering Committee Contractor/Sponsors: European University Foundation and Ministry of Culture, Higher Education and Research (Luxembourg).  Allianz Kulturstiftung, Volkswagen Stiftung, Herbert-Quandt-Stiftung (Germany). Period: March 2002 - 2004 Web page of the project: http://www.campuseuropae.org/en/ and http://arantxa.ii.uam.es/~europae/ Project Title: "Sistems of Reconfigurable Computing on FPGAs (SCORE): Analysis of Themal Aspects" Duties: UAM Project Director Contractor: Conserjería de Educación, Comunidad Autónoma de Madrid, Project 07T/0052/2003 3 Period: 2003 - 2004 Technology: Xilinx FPGAs. Project Title: "GEMYC: Management of Emergencies and Communications" Duties: Project Director Contractor: Fedetec (Madrid, Spain). Partners: Iaerobotics (Madrid, Spain). Period: 2002-2003. Project Summary: Small capability PCI System for emergency centers. Currently working at the Spanish "112" emergency call.  Voice-Data PBX with Basic ISDN access capability. H100 Standard compatible. Technology: Agere chipset, Xilinx FPGAs and PLDs. Project Title:"Design of IP-Cores for Wireless Commnucations based on OFDM. Low Power Optimization of the mobile units" Duties: Project Director Contractor: Programa Nacional de Comunicaciones (CICYT and DGT, Spain). TIC2001-2688-C03-03 Period: 2001-2003 Technology: Xilinx FPGAs. Project Title: Integrated B2B E-Commerce Systems Duties: Project Director Contractor: Cecofersa (Alcobendas, Spain). Partners: Inetsys (Madrid, Spain). Period: 2000-2001. Project Summary: Internet portal for B2B in the area of construction hardware. It concentrates the activities of more than one hundred SMEs. Technology: Linux. Web page of the project: http://www.comprabuena.com Project Title: "Multiplier Effect Project : EUROFORM - European Training Institute" Contractor: Leonardo Program, European Union. Contract: F/99/1/062137/PI/III.3.a/FPC. Period: 1998-2000. Project Summary: Technical training and assistance for SMEs in the area of electronic system design. Web page of the project: http://www.ii.uam.es/~euroform/  and http://www.mee.tcd.ie/research_groups/ic_design_fab/euroform/ . Project Title: "Student Placement: EUROFORM - European Training Institute" Contractor: Leonardo Program, European Union. Contract: F/99/07144/PL/II.1.2.a/FPI Period: 1999-2000. Project Summary: Placement of graduated students in european SMEs. Web page of the project: http://www.ii.uam.es/~euroform/  and http://www.mee.tcd.ie/research_groups/ic_design_fab/euroform/ Project Title: Digital Communication Integrator Board: Modification of DMA Contractor: FEDETEC (Madrid, Spain). Period: 2000. Project Summary: Hardware modification to increase DMA bandwidth of a ISA Voice-Data PBX with Basic ISDN access capability. MVIP Standard compatible. Technology: Mitel chipset, Xilinx FPGAs and PLDs. Project Title: PCI Architecture for a Digital Communication Integrator Board Duties: Project Director Contractor: Fedetec (Madrid, Spain). Partners: Microbótica (Madrid, Spain). Period: 1999-2001. Project Summary: PCI Voice-Data PBX with Basic ISDN access capability. H100 Standard compatible. Technology: Agere chipset, Xilinx FPGAs and PLDs, DSP Texas. Projects at the ETSI Telecomunicacion - UPM (1989-1996) Project Title: "COMA: A Methodology for Synthesis, Design, and Evaluation of VLSI Architectures for Video Image Coding". Duties: R&D Engineer Contractor: Programa Nacional de Comunicaciones (CICYT and DGT, Spain). Project TIC-95-0791. Period: 1995-1998. Technology: Xilinx and Altera FPGAs, ES2 Standard Cells. Project Title: "A Methodology for the Desing and Synthesis of DSP VLSI Arcuitectures" Duties: R&D Engineer Contractor: Programa Nacional de Comunicaciones (CICYT and DGT, Spain). Project TIC-92-0083. Period:1992-1995. Technology: Xilinx and Altera FPGAs, ES2 Standard Cells. Project Title: "Digital Communication Integrator Board" Contractor: Fedetec, (Madrid, Spain). Period: 1996. Project Summary: Design and construction of a PC-based Voice-Data PBX with Basic ISDN access capability. MVIP Standard compatible. Technology: Mitel chipset, Xilinx FPGAs, Microprocessor Motorola MC68302. Project Title: "TALGO: Design of an ASIC for the control of Audio Channels". Contractor: SIDSA, Spain. Period: 1993-94. Project Summary: Design of a mixed-signal integrated circuit for audio TDM demultiplexing (four analog channels), and volume control. The chip is currently utilized on spanish Talgo trains. More than 30K units have been fabricated. Technology: 1.5 m ES2 Standard Cells, SOLO 1400. Project Title: "Massive Solid-State Memory for On-Board Satellite Applications". Contractor: Alcatel Space. Period: 1993. Project Summary: Design of a low-power, graceful-degradation , 2-Gbytes , 150-Mbits/seg memory bank. Technology: Hard-Rad standard components. Project Title: VITA ("Video Telephone Alcatel"). Contractor: ALCATEL-SESA, Spain. Period: 1990-91. Project Summary: Design and construction of a two boards for Raster Scan to CIF CCIR 605 conversion and vice versa. Technology: Standard off-the-shelf components, PLDs, Xilinx FPGAs. Project Title: "CAD Tools for the Design of Systolic Arrays". Contractor: IBM Spain. Period: 1990-91. Project Summary: EDA tools for Synthesis and Simulation of Systolic Architectures. Project Title: HIVIT ("High Quality Video Telephony"). Contractor: Telefónica I+D, Spain. Period: 1989-90. Project Summary: Design and construction of a board for Variable Length Video Decoding. Technology: Standard off-the-shelf components, PLDs. Last update: FEB11