We can make 4x16 decoders using 2x4 decoders in two ways :
Only one level of decoders is used in this topology. The input vector is divided in several subvectors that are the inputs of the modules.
In the example, the 4 input bits are divided in two subvectors ( x4, x3 ) and ( x2, x1 ) . Every decoder returns 8 minterms of 2 variables each. What we want is to obtain the 16 minterms of the 4 input variables. For that purpose, we put 16 and gates. The first input of the and gate gathers a minterm of the first 2 variables, and the second one of the remainder two. The circuit is shown in the following figure ( the last input of the first line is the enabled bit ).
For example : Y6 = left_decoder.Y1 and right_decoder.Y2, becouse the 6th minterm = ( x4' x3 x2 x1' ).
Two levels of decoders is necessary. The input variables are divided in two groups. The first group is the input of the first level decoder, and the second group is the input of the second level decoders.
The outputs of the first decoder are the enabled bits of the second level decoders. You can see the circuit in the following figure :
The tree scheme is better than the other one in terms of number of chips and connections.
Last modified 1/1/2000 by Juan de Lara ( Juan.Lara@ii.uam.es, http://www.ii.uam.es/~jlara) need help for using this courses?.